2026-03-11T10:40:20Z https://kitakyu.repo.nii.ac.jp/oai

oai:kitakyu.repo.nii.ac.jp:00000779 2026-01-31T02:08:43Z 11:10

Density Optimization for Analog Layout based on Transistor-array トランジスタ・アレイ方式に基づくアナログレイアウトにおける密度最適化 ゴン, チャオ open access analog layout design for manufacturability layout density transistor array algorithm design In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus on a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile, it shows a good circuit performance in the post-layout simulation. eng doctoral thesis VoR https://kitakyu.repo.nii.ac.jp/records/779 甲第151号 博士（工学） 2020-09-26 27101 北九州市立大学 https://kitakyu.repo.nii.ac.jp/record/779/files/(KKDE1151GC)甲第151号_ｺﾞﾝ ﾁｬｵ.pdf application/pdf 6.0 MB 2020-12-24