{"created":"2023-06-19T07:56:50.828950+00:00","id":412,"links":{},"metadata":{"_buckets":{"deposit":"81af1938-46ad-4b53-b63a-61004a70e8f1"},"_deposit":{"created_by":14,"id":"412","owners":[14],"pid":{"revision_id":0,"type":"depid","value":"412"},"status":"published"},"_oai":{"id":"oai:kitakyu.repo.nii.ac.jp:00000412","sets":["11:10"]},"author_link":["471","472"],"control_number":"412","item_10006_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"ポータビリティを意識したCMOSミックスドシグナルVLSI回路設計手法に関する研究","subitem_alternative_title_language":"ja"}]},"item_10006_date_granted_11":{"attribute_name":"学位授与年月日","attribute_value_mlt":[{"subitem_dategranted":"2014-09-26"}]},"item_10006_degree_grantor_9":{"attribute_name":"学位授与機関","attribute_value_mlt":[{"subitem_degreegrantor":[{"subitem_degreegrantor_name":"北九州市立大学"}],"subitem_degreegrantor_identifier":[{"subitem_degreegrantor_identifier_name":"27101","subitem_degreegrantor_identifier_scheme":"kakenhi"}]}]},"item_10006_degree_name_8":{"attribute_name":"学位名","attribute_value_mlt":[{"subitem_degreename":"博士(工学)"}]},"item_10006_description_7":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"本研究は、半導体上に集積されたアナログ・ディジタル・メモリ回路から構成されるミクストシグナルシステムを別の製造プロセスへ移行することをポーティングとして定義し、効率的なポーティングを行うための設計方式と自動回路合成アルゴリズムを提案し、いくつかの典型的な回路に対する設計事例を示し、提案手法の妥当性を立証している。","subitem_description_type":"Abstract"}]},"item_10006_dissertation_number_12":{"attribute_name":"学位授与番号","attribute_value_mlt":[{"subitem_dissertationnumber":"甲第76号"}]},"item_10006_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"472","nameIdentifierScheme":"WEKO"}],"names":[{"name":"チョウ, ウ"}]}]},"item_10006_version_type_18":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yu ZHANG","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"471","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2014-12-14"}],"displaytype":"detail","filename":"(KKDE1076CU)甲76号チョウウ.pdf","filesize":[{"value":"2.6 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"(KKDE1076CU)甲76号チョウウ","objectType":"fulltext","url":"https://kitakyu.repo.nii.ac.jp/record/412/files/(KKDE1076CU)甲76号チョウウ.pdf"},"version_id":"4de2976b-7010-46e1-b2e8-16b79095edb9"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"layout-dependent effects(LDE)","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"shallow trench isolation(STI)","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"well proximity effect(WPE)","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"integrated circuit","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"VLSI","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"geometric programming(GP)","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"delay locked loop circuit(DLL)","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"standard cell","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"memory","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"parameterized cell","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"doctoral thesis","resourceuri":"http://purl.org/coar/resource_type/c_db06"}]},"item_title":"Portability-Aware CMOS Mixed Signal VLSI Circuit Design Methodology","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Portability-Aware CMOS Mixed Signal VLSI Circuit Design Methodology","subitem_title_language":"en"}]},"item_type_id":"10006","owner":"14","path":["10"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2014-12-14"},"publish_date":"2014-12-14","publish_status":"0","recid":"412","relation_version_is_last":true,"title":["Portability-Aware CMOS Mixed Signal VLSI Circuit Design Methodology"],"weko_creator_id":"14","weko_shared_id":-1},"updated":"2024-04-12T04:39:25.158154+00:00"}