{"created":"2023-06-19T07:57:09.146772+00:00","id":779,"links":{},"metadata":{"_buckets":{"deposit":"71f12071-f3fc-47d6-a34a-37d042c93f02"},"_deposit":{"created_by":14,"id":"779","owners":[14],"pid":{"revision_id":0,"type":"depid","value":"779"},"status":"published"},"_oai":{"id":"oai:kitakyu.repo.nii.ac.jp:00000779","sets":["11:10"]},"author_link":["912"],"control_number":"779","item_10006_alternative_title_1":{"attribute_name":"その他（別言語等）のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"トランジスタ・アレイ方式に基づくアナログレイアウトにおける密度最適化","subitem_alternative_title_language":"ja"}]},"item_10006_date_granted_11":{"attribute_name":"学位授与年月日","attribute_value_mlt":[{"subitem_dategranted":"2020-09-26"}]},"item_10006_degree_grantor_9":{"attribute_name":"学位授与機関","attribute_value_mlt":[{"subitem_degreegrantor":[{"subitem_degreegrantor_name":"北九州市立大学"}],"subitem_degreegrantor_identifier":[{"subitem_degreegrantor_identifier_name":"27101","subitem_degreegrantor_identifier_scheme":"kakenhi"}]}]},"item_10006_degree_name_8":{"attribute_name":"学位名","attribute_value_mlt":[{"subitem_degreename":"博士（工学）"}]},"item_10006_description_7":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus on a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile, it shows a good circuit performance in the post-layout simulation.","subitem_description_type":"Abstract"}]},"item_10006_dissertation_number_12":{"attribute_name":"学位授与番号","attribute_value_mlt":[{"subitem_dissertationnumber":"甲第151号"}]},"item_10006_version_type_18":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"ゴン, チャオ","creatorNameLang":"ja"}],"nameIdentifiers":[{"nameIdentifier":"912","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2020-12-24"}],"displaytype":"detail","filename":"(KKDE1151GC)甲第151号_ｺﾞﾝ ﾁｬｵ.pdf","filesize":[{"value":"6.0 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"(KKDE1151GC)甲第151号_ｺﾞﾝ ﾁｬｵ","objectType":"fulltext","url":"https://kitakyu.repo.nii.ac.jp/record/779/files/(KKDE1151GC)甲第151号_ｺﾞﾝ ﾁｬｵ.pdf"},"version_id":"a9047568-9115-441a-9567-fee3a6e96bb3"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"analog layout","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"design for manufacturability","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"layout density","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"transistor array","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"algorithm design","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"doctoral thesis","resourceuri":"http://purl.org/coar/resource_type/c_db06"}]},"item_title":"Density Optimization for Analog Layout based on Transistor-array","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Density Optimization for Analog Layout based on Transistor-array","subitem_title_language":"en"}]},"item_type_id":"10006","owner":"14","path":["10"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2020-12-24"},"publish_date":"2020-12-24","publish_status":"0","recid":"779","relation_version_is_last":true,"title":["Density Optimization for Analog Layout based on Transistor-array"],"weko_creator_id":"14","weko_shared_id":-1},"updated":"2024-04-09T01:21:21.194493+00:00"}