@phdthesis{oai:kitakyu.repo.nii.ac.jp:00000780,
 author = {ズオウ, シュンチャン},
 month = {2020-12-24},
 note = {This work presents a fully synthesizable stochastic flash A/D converter (SFADC), which can operate at the supply voltage of 0.6V with power consumption as low as 1.5mW at the clock frequency of 250MHz. By employing the all-digital comparator, the SFADC can be described with Verilog netlist and synthesized according to a standard digital design flow. Cross-coupled dynamic comparator structure saves the overall power due to remarkable control of dynamic power consumption. In addition, the rail-to-rail characteristic of comparator and the proposed linearity enhancement technique based on SFADC are proposed, allowing us to design a wide input-range stochastic flash ADC.},
 school = {北九州市立大学},
 title = {A Fully Synthesizable, Low Voltage and Low Power Stochastic Flash A/D Converter with Wide Input Range},
 year = {}
}